1. Field of the Invention
The present invention relates to a method and apparatus for providing direct access by an external data processing system to data stored in the main memory of a host system, and more particularly, to an interface method and apparatus for providing direct memory access by an external data processing system such as a graphics subsystem to physical memory of the host system by establishing work buffers in main memory of the host system for each user process and transferring data from the work buffers to the external data processing system under the user's control.
2. Description of the Prior Art
Generally, data transfer between the processor of a host system and an external data processing device is performed via an input/output (I/O) attachment under direct control of a program being run by the host processor. Typically, each byte or word of data requires the execution of several instructions to transfer. However, some I/O devices require higher data transfer rates than are achievable with this technique. For such devices, the I/O attachment may use a data transfer process known as direct memory access (DMA). DMA allows the direct transfer of data between the host processor memory and the I/O attachment without the necessity of executing instructions in the host processor. In particular, during DMA the host processor first initializes the DMA controller circuitry by storing a count and a starting memory address in its registers. Once started, DMA proceeds without further host processor intervention (except that an interrupt may be generated upon completion of the DMA operation), and hence data transmission is handled without the need to execute further instructions in the host processor.
I/O attachments using such a DMA technique are known and generally incorporate circuitry of the type shown in FIG. 1. The host processor of the DMA controller of FIG. 1 sets the address counter and counter registers 10 and 12. The signal Bus Cycle is assumed to define the interval of time during which the addresses are presented and data are exchanged on the bus. The DMA controller also connects to the I/O attachment with the lines Transmit Request and Request Granted. During operation, when the I/O attachment wishes to use a bus cycle, it raises the voltage on the line Transmit Request. If the DMA count register 12 is nonzero, the signal is placed on the Bus Request line to the host processor. The host processor hardware periodically examines this signal, and when it is of a high logic level the host processor waits until the end of the current bus cycle, stops, places its address and data line drivers in the high-impedance state, and raises the voltage of the line Bus Grant. The host processor is thus effectively isolated from the bus during bus cycles granted to the DMA controller. When a high logic level of Bus Grant is sensed by the DMA controller, it places the contents of its address counter register 10 on the Address lines and signals the I/O attachment on Request Granted that it may use the current bus cycle for transmission of data. The I/O attachment itself may thus drive the bus lines that determine the direction of data transfer, or additional circuitry in the DMA controller may drive these lines. As long as Transmit Request is held at a high logic level, consecutive bus cycles may be used by the I/O attachment. Such a technique is known as "cycle stealing".
The circuitry of prior art FIG. 1 is capable of using successive bus cycles ("burst mode") or using bus cycles intermittently. The choice depends on the data transfer rate of the I/O attachment. In fact, the processor of the host system often must use several bus cycles in preparation for relinquishing the bus by generating Bus Grant, and must use several bus cycles after regaining the bus. These cycles are unproductive in that they do not contribute to instruction execution or data transfer. Therefore, DMA transfers that use consecutive bus cycles make more efficient use of the bus.
Thus, in order to reduce the load on the host processor when transferring data to an external data processing system, it is known to use DMA to fetch data from the main memory of the host system and to pass it to the external data processing system without requiring additional processor instructions. However, such prior art DMA techniques have been typically initiated by the kernel software in the host processor to guarantee the integrity of multi-user memory space and have not been initiated by an unprivileged user process of the host system. As a result, when a user application program of the host system calls for processing of large blocks of data as in conventional graphics processing or networking systems, user scheduled DMA has not been possible. Rather, access to the main memory of the host system has been typically provided through operating system or kernel software control in the host processor, thereby significantly slowing the overall data transfer time of the system and complicating user programming. Hence, it has heretofore been extremely difficult to perform real-time manipulations of graphics and other such complex data profiles under user direction.
Accordingly, there is a long-felt need for a process and apparatus which enables an external process to access data in the main memory of a host system under user control whereby the time required for data transfer to the external process or data processing system can be substantially reduced so as to allow real-time data manipulation without losing system security. The present invention has been designed for this purpose.